tdcp.py

Created on May 11, 2023
882 Bytes
1. Écrivez en VHDL (entité et architecture) correspondant au circuit sch_complet 

Entity SCH_complet is
port(A,B,C,D: in STD_logic ;
T out_std_logic);
End sch_complet;

architecture arch sch_complet of sch_complet is
begin
T<= (A and B) on (C and D);
end arch sch_complet;

2. a. Porte ET

Entity porte_et is 
port(E1,E2:in STD_logic;
S: out_STD_logic);
End porte_et;

architecture arch_porte_et of porte_et is
Begin
S<=(E1 and E2);
End arch porte_et;

2. b. Pareil avec porte ou (or)

c. Entité et architecture structurelle
Architecture arch 2 of sch_complet is
signal S1, S2: STD_logic;
component porte_et
port(E1,E2 : in STD_logic ; S: out STD_logic),
End component;
component porte_on
Port (_O1,_02 : in STD_logic; R:out std_logic),
End component;

begin

C1:porte_et port map (E1=>A,E2=>B,S=>S1);
C2: porte_et port map(C,D,S2);
C3:porte_ou port map(S1,S2,T);