rattrapages_elec.py

Created by famille-bvc

Created on March 03, 2023

2.74 KB


 ** Transistors Bipolaires **

 * Montage emetteur commun *

 Schéma général en NPN :
            _______ +Vcc
            |     |
           R1    Rc   
            |   __|___Cl_..._
            | |/             |
 -Rs-...-Cl---|              |
 |          | |\________     |
(s)         |     |    |    Rl
 |         R2     Re   Ce    | 
 |          |     |    |     |
Gnd        Gnd   Gnd  Gnd   Gnd

(s) -> generateur sinusoïdale

Schéma statique :
  
          _________ +Vcc
          |       |
         R1       Rc
          |     __|
          |   |/v Ic0 ^
          |->-|       | Uce0
          |Ib0|\v__   |
          |       | 
         R2 <---- Re
          |  Ube0 |
         Gnd     Gnd
* -> rep

*Ic0 = βIb0

Rth = R1//R2
             R2
Eth = Vcc --------
           R1 + R2
Eth = Re Ico + Vbeo + Rth Ibo

        Eth - Vbeo
*Ibo = ------------
        β Re + Rth
        
Vcc = Re Ic0 + Vce + Rc Ic0

*Uce0 = Vcc - Ic0 (Re + Rc)

*Droite de charge statique
-> x = Vcc - y (Re + Rc)

Schéma Dynamique
                    ib       βib   ic
     --Rs-...-------->--    --<----<---...--
  ^  |       |    |    |    /\   |    |    |  ^
Ve| (s)      R2   R1  h11   \/   ρ    Rc   Rl |Vs
  |  |       |    |    |   +|    |    |    |  |
     -----...--------------------------...--
     
h11 et ρ -> Resistance
? -> en fonction du schéma

        -β (Rc // ρ // Rl?)
*gain = -------------------
                h11
               
*Droite de charge statique
dynamique -> y = -x /(Rc // Rl)

*Zen = (R2 // R1 // h11) + Rs?

*Zs = (Rc // ρ // Rl?)

#/////////////////////////////
** Transistors JFET **

* Montage source commune *

Schéma général :
                 ___ +Vcc
                  |
                  RD 
                  |
               |------C2-...-|
 --...--C1---->|             |           
 |          |  |-------      |
 Rg         |     |   |      |
 |          |     |   |      |
(s)eg(t)    RG    Rs  Cs     Rl
 |          |     |   |      |
Gnd        Gnd   Gnd Gnd    Gnd

Schéma statique :
  
                --- +Vcc
                 |
                 RD
                 |v ID
       IG G  |---.D  ^
      -->-.->|       |VDS
      |      |---.S  |
      |    <---- |v Is
      RG    VGS  Rs
      |          |
     Gnd        Gnd
     
*IG0 = 0
                 VGS
*ID0 = IDSS (1 + ----)^2
                 |Vp|

*VGS0 = -Rs Id0

*VDS0 = Vcc/2

Vcc = Rs Id0 + VDS0 + RD ID0
Rs ID0 + VGS0 = 0

Schéma dynamique :
  
  ---...--------      ----------------...--
  Rg      |    ^      |        ^     |    |
  |       |    |     |O gmVGS  |     |    |
 (s)eg(t) RG   |VGS  vO        |VDS  RD   Rl
  |       |    |      |        |     |    |
  ---...------------------------------...--
  
*gain = -gm (Rd // Rl?)

*Zen = RG

*Zs = RD

During your visit to our site, NumWorks needs to install "cookies" or use other technologies to collect data about you in order to:

With the exception of Cookies essential to the operation of the site, NumWorks leaves you the choice: you can accept Cookies for audience measurement by clicking on the "Accept and continue" button, or refuse these Cookies by clicking on the "Continue without accepting" button or by continuing your browsing. You can update your choice at any time by clicking on the link "Manage my cookies" at the bottom of the page. For more information, please consult our cookies policy.