cprog_td1.py

Created by famille-bvc

Created on May 11, 2023

1.25 KB


1. Ecrivez en langage VHDL le programme (entité et architecture ) correspondant 
à la réalisation du circuit sch_complet. Ce programme doit-être le plus simple
possible.


Entity sch_complet si
Port (A, B, C, D : in STD_LOGIC;
T : out STD_LOGIC);
End;

Architecture sch_complet_arch of sch_complet is

Begin
T <= (A and B) or (C and D);
End;

/////////////////////////////
2.a Ecrivez en langage VHDL le programme (entité et architecture ) 
correspondant à la réalisation d'une porte ET (E1, E2, S ) prise seule. 
L'entité sera appelée porte_ et.


Entity port_et is
Port (E1, E2 : in std_logic;
S : out std_logic);
End;

architecture arch of porte_et is

Begin
S <= E1 and E2;
End;

/////////////////////////////
2.c Ecrivez en langage VHDL le programme (entité et architecture structurelle)
correspondant à la réalisation du circuit sch_complet.


architecture arch2 of sch_complet is

  Signal s1, s2 : std_logic;
  Component porte_et
    Port (E1, E2 : in std_logic;
      S : out std_logic);
  End component;

  Component porte_ou
    Port (_O1, O2 : in std_logic;
  R : out std_logic);
  End component;

Begin
  C1 : porte_et port map ( E1 => a, E2 => b, S => S1);
  C2 : porte_et port map (c, d, S2);
  C3 : porte_ou port map (S1, S2, T);
End;

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