grizdal.py

Created on May 01, 2024
1.93 KB
%Logique combinatoire: 
1) Circuit sch_complet
entity sch_complet is
  port(A,B,C,D : in std_logic;
       T : out std_logic);
end;

architecture sch_complet_arch of sch_complet is
  begin
    T<= (A and B)  or (C and D);

end;

2) Interieur circuit sch_complet avec différnets composants

entity porte_ET is 
  port(E1,E2: in std_logic;
  S: out std_logic);
end

architecture arch of porte_ET is
  begin
    S<= (E1 and E2);
end;

entity porte_OU is
  port(O1,O2 : in std_logic;
       R: out std_logic);
end

architecture arch of porte_OU is
  begin
    R<= (O1 or O2);
end; 


architecture arch2 of sch_complet is
  signal S1,S2;
  component porte_ET
    port (E1,E2 : in std_logic;
          S : out std_logic);
  end component;
  
  component porte_OU
    port(O1,O2 : in std_logic;
         R : out std_logic);
  end component;
  
  begin
    C1: porte_ET port map (A,B,S1);
    C2:porte_ET port map (C,D,S2);
    C3:porte_OU port map (S1,S2,T);
end
    
    
%encodeur 1 parmi 4

entity encodeur1_4 is
port(C : in std_logic_vector(1 downto 0) ;
     S : in std_logic_vector(3 downto 0));
end;

architecture arch1 of encodeur1_4 is 
  begin
    with C select
    S<="0001" when "00",
       "0010" when "01",
       "0100" when "10",
       "1000" when "11",
       "0000" when others;
      %"S3,S2,S1,S0" when "C1,C0"%
end;


% registre à décalage

entity sreg is
port(s_i : in std_logic ;
     s_o : out std_logic ;
     Q : out std_logic_vector(3 downto 0)) ;
end;

architecture arch of sreg is
signal d : std_logic_vector(3 down to 0) ;  
begin
    process(clk)
    begin if(clk event and clk'1') then
      d<=d(2 down to 0) & s_i;
      end if;
  end process;
    Q<=d;
    s_o<=d(3);
  end;


%transceiver

entity transceiver is 
  port(OEAB,OEBA : in std_logic;
       A,B : in std_logic_vector (7 downto 0));
end; 

architecture arch of transceiver is
begin
  A<=B when OEBA ='1' else "zzzzzzzz"
  B<=A when OUAB ='1' else "zzzzzzzz");
end;